1. Field of the Invention
This invention relates to Baseband Processor and Error-Correction Codes for Third Generation (3G) Wireless Mobile Communications; and more particularly, the invention relates to a very high speed Turbo Codes Decoder using pipelined Log-MAP decoders method for for Third Generation (3G) CDMA2000 and 3G-WCDMA.
2. Description of Prior Art
Turbo Codes decoding is based upon the classic forward error correction concepts that include the use of recursive systematic constituent Encoders (RSC) and Interleaver to reduce Eb/N0 for power-limited wireless applications such as digital 3G Wireless Mobile Communications. A Turbo Codes Decoder is an important part of the baseband processor in the wireless communication Receiver, which is used to reconstruct the corrupted and noisy received data and to improve BER (bit-error-rate) throughput. FIG. 1. shows an example of a 3G Receiver with a Turbo Codes Decoder 13 which decodes data from the Demodulator 11 and De-mapping 12 modules, and sends decoded data to the MAC layer 14. FIG. 2. shows an example of an 8-PSK constellation points 21 produced by the Demodulator module 11. The De-mapping 12 module uses the 8-PSK constellation points 21 to convert into binary data 22 and send to the Turbo Codes Decoder 13. The data 22 is then decoded and reconstructed by the Turbo Codes Decoder 13 and send to the MAC layer 14.
A most widely used forward-error-correction FEC scheme is the Viterbi Algorithm Decoder in both wired and wireless application. A drawback is that it requires a long waiting for decisions until the whole. sequence has been received. A delay of six time the memory length of the received data is required for decoding. One of the more effective FEC, with higher complexity, a MAP algorithm used to decode received message has comprised the steps of very computational complex, requiring many multiplications and additions per bit to compute the posteriori probability. A major difficulty with the use of the MAP algorithm has been the implementation in semiconductor ASIC devices, the complexity the multiplications and additions which will slow down the decoding process and reducing the throughput data rates. Furthermore, even under the best conditions, each operations used in the MAP algorithm requires a large circuits in the ASIC. The result is costly, and low performance in bit rates throughput.
Recently introduced by the 3GPP organization a new class of codes using parallel concatenated codes (PCCC) that include the use of the classic recursive systematic constituent Encoders (RSC) and Interleaver as shown in FIG. 3. offers great improvement. An example of the 3GPP Turbo Codes PCCC Turbo Codes with 8-states and rate ⅓ is shown in FIG. 3. data enters the two systematic encoders 3133 separated by an interleaver 32. An output codeword consists of the source data bit followed by the parity check bits of the two encoders. Other prior work of error correction codes was done by Berrou et al. describing a parallel concatenated codes which is are much complex encoding structure that are not suitable for portable wireless device. Another patent U.S. Pat. No. 6,023,783 by Divsalar et al. describes a more improved encoding method than Berrou using some basic mathematical concepts of parallel concatenated codes. However, patents by Berrou, the U.S. Pat. No. 6,023,783, and others only describe the basic concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects but are not feasible, economical, and practical for consumers. The encoding of data is simple and can be easily implemented with a few xor and flip-flop logic gates. But the decoding the Turbo Codes is much more difficult to implement in ASIC or software. The prior arts describe briefly the implementation of the Turbo Codes Decoder which are mostly for deep space communications and requires much more hardware, powers and costs.
All the prior arts of Turbo Codes fail to achieve a simpler method for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices including high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environment.
The present invention directed Turbo Codes Decoder to implement a more efficient, practical and simpler method to achieve the requirements for 3G cellular phones and 3G personal communication devices including higher speed data throughput, lower power consumptions, lower costs, and simpler implementation in ASIC or software. The present invention encompasses improved and simplified Turbo Codes Decoder method and apparatus to deliver higher speed and lower power especially for 3G applications. An exemplary embodiment Turbo Codes Decoder utilizes two pipelined and serially concatenated SISO Log-MAP Decoders with Interleaver-Memory at the output of the first decoder and a De-interleaver-Memory at the second decoder. The two decoders function in a pipelined scheme with delay latency N; while the first decoder is decoding data in the de-interleaver-Memory, the second decoder performs decoding data in the interleaver-Memory, which produces a decoded output every clock cycle in results. Accordingly, several objects and advantages of our Turbo Codes Decoder are:
To deliver higher speed throughput and lower power consumption
To utilize SISO Log-MAP decoder for faster decoding and simplified implementation in ASICr with the use ofbinary adders for computation.
To perform re-iterative decoding of data back-and-forth between the two Log-MAP decoders in a pipelined scheme until a decision is made. In such pipelined scheme, a decoded output data is produced each clock cycle.
To improve higher performance in term of symbol error probability and low BER for 3G applications such as 3G W-CDMA, and 3G CDMA2000 operating at very high bit-rate up to 100 Mbps in a low power noisy environment.
To utilize an simplified and improved architecture ofSISO Log-MAP decoder including branch-meric (BM) calculations module, recursive state-metric (SM) forward/backward calculations module, Log-MAP posteriori probability calc ulations module, and output decision module.
To reduce complexity of multiplier circuits in MAP algorithm by perform the entire MAP algorithm in Log domain with the uses of binary der circuits which are more suitable for ASIC implementation while still maintain a high level of performance output.
To design an improve Log-MAP Decoder using high level design language of VHDL which can be synthesized into custom ASIC and FPGA devices.
Still further objects and advantages will become apparent to one skill in the art from a consideration of the ensuing descriptions and accompanying drawings.